1. Field of the Invention
The present invention relates to processors and processor stacks. More specifically, the present invention relates to a fast stack save and restore apparatus for a processor.
2. Description of the Related Art
In a computer or processor, a stack is a sequential data list stored in internal storage. A processor retrieves information from the stack by popping elements from the top of the stack in a last-in-first-out (LIFO) system or from the bottom of the stack in a first-in-first-out (FIFO) system, and stores information onto the stack by pushing elements to the stack. In contast, other storage structures are accessed simply by addressing individual elements by memory location.
A processor may utilize a stack that is stored in a plurality of locations in a storage such as a system memory. In other processors, a stack may be held within several dedicated registers. Under certain circumstances, such as a context switch of a processor, the stack is saved to preserve the processor context for a subsequent return to processing.
A processor typically performs a stack save operation by reading each entry in the stack and individually moving the entries to a save area. Similarly, the processor typically restores the stack by relocating each stack entry in the save area back to the stack while maintaining the original entry order relationship. Therefore a typical processor performs a save stack operation by reading the stack storage and writing each stack element into a save area of memory. The typical processor performs a restore stack operation by accessing single elements in the save area of memory and restoring each accessed stack element to the stack storage.
For example, a typical processor saves an eight entry stack through the execution of sixteen or more instructions. The sixteen or more instructions utilized by the typical processor include eight read operations of reading a stack entry into a temporary storage and writing the temporary storage to a stack save storage. A typical processor restores the eight element stack using another sixteen instructions, thirty-two operations for an overall read and restore operation.
Processor architectures are continually evolving to improve and extend the capabilities of computer systems. Execution speed, power consumption, and circuit size are aspects of processors and processor performance that are constantly addressed by architects and designers in the ongoing quest for an improved product.
Personal computers (PC""s) such as microcomputers have gained widespread use in recent years primarily because they are inexpensive and yet powerful enough to handle computationally-intensive user applications. Data storage and data sharing functions of personal computers are often expanded by coupling a group of such computers to peripheral devices such as disk drives, tape drives, and printers. The peripheral devices and the personal computers are interconnected through a single communications network, such as a local area network.
The group of computers is coupled using interfaces that facilitate and accelerate communications among the computers and peripheral devices. A host adapter is a common interface device that is used to connect a first bus that has a specified protocol for transferring information over the first bus and a first data transfer speed to a second bus. The second bus also has a specified protocol for transferring information over the second bus at a second data transfer speed. The host adapter operates to transfer information between the first bus and the second bus.
A primary consideration of the performance of a network interface is data transfer speed. For an intelligent network interface that includes a processor for controlling and monitoring information transfer, execution speed of the processor is paramount. While the execution speed of the processor is fundamentally based on the clock speed of the processor, other aspects of processor performance may also strongly influence effective performance.
For example, for a processor within a network interface that includes a stack, the time expended for context switching may be highly determinative of effective data transfer speed.
What is needed is a system and technique for improving context switching speed of a processor by reducing the number of instructions that are executed during saving and restoring of a stack.
A processor includes a stack that operates as a circular stack and appears to the address space in the memory of the processor as a single point address location. The stack supports read and write data access functions in addition to CALL (push) and RETURN (pop) programming operations. The processor may be programmed to save the stack in a typical manner with one instruction automatically transferring each element in the stack directly from the stack to a save storage. To restore the stack, the processor may be programmed to individually restore each element.
The processor supports a special MOV instruction that transfers a plurality of bytes in a single operation. The special MOV instruction has one argument that identifies the beginning transfer source address, another argument defines the byte count indicating the number of bytes to be transferred, and a beginning transfer destination address. The processor may be programmed to perform a stack save operation with only a single instruction that moves the contents of the stack to the save storage.
To further reduce context switching time and reduce the stack save and restore operation to a minimum number of instructions while maintaining the proper entry relationship for both stack read and write operations, the processor includes a xe2x80x9cstack read forwardxe2x80x9d option to the special MOV instruction. The option to the special MOV instruction operates to read data in a forward direction, the direction used when writing, even when no valid data may be stored in the locations. The read operation begins at the current stack write address pointer, reading forward causes the stack write pointer to increment, and wraps around in a binary fashion back to the initial address when the MOV instruction completes.
In an illustrative embodiment, a SAVSTKRDEN bit of a SEQCTL register is assigned that, when set, enables the save stack read operation to be performed with the MOV instruction of the processor. The SAVSTKRDEN bit is automatically cleared when the MOV count expires so that an additional instruction for clearing the bit is eliminated. In other embodiments, a bit in other registers may be utilized to control a forward read operation. In further additional embodiments, for example when a spare address space is available, one address may be assigned that enables the save stack read operation.